Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design

Yuya KITAZAWA
Kazuhito ITO

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E105-A    No.3    pp.530-539
Publication Date: 2022/03/01
Publicized: 2021/09/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.2021VLP0015
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
double modular redundancy,  register minimization,  soft error,  LSI design,  

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Summary: 
Double modular redundancy (DMR) is to execute an operation twice and detect a soft error by comparing the duplicated operation results. The soft error is corrected by re-executing necessary operations. The re-execution requires error-free input data and registers are needed to store such necessary error-free data. In this paper, a method to minimize the required number of registers is proposed where an appropriate subgraph partitioning of operation nodes are searched. In addition, using the proposed register minimization method, a minimization of the area of functional units and registers required to implement the DMR design is proposed.