
For FullText PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.

LowPower Implementation Techniques for Convolutional Neural Networks Using Precise and Active Skipping Methods
Akira KITAYAMA Goichi ONO Tadashi KISHIMOTO Hiroaki ITO Naohiro KOHMU
Publication
IEICE TRANSACTIONS on Electronics
Vol.E104C
No.7
pp.330337 Publication Date: 2021/07/01 Publicized: 2020/12/22 Online ISSN: 17451353
DOI: 10.1587/transele.2020CDP0003 Type of Manuscript: Special Section PAPER (Special Section on SolidState Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: convolutional neural network (CNN), SSD500 network, deep neural network (DNN) implementation, low power consumption, embedded AI technique,
Full Text: FreePDF(3.3MB)
Summary:
Reducing power consumption is crucial for edge devices using convolutional neural network (CNN). The zeroskipping approach for CNNs is a processing technique widely known for its relatively low power consumption and high speed. This approach stops multiplication and accumulation (MAC) when the multiplication results of the input data and weight are zero. However, this technique requires large logic circuits with around 5% overhead, and the average rate of MAC stopping is approximately 30%. In this paper, we propose a precise zeroskipping method that uses input data and simple logic circuits to stop multipliers and accumulators precisely. We also propose an active dataskipping method to further reduce power consumption by slightly degrading recognition accuracy. In this method, each multiplier and accumulator are stopped by using small values (e.g., 1, 2) as input. We implemented single shot multibox detector 500 (SSD500) network model on a Xilinx ZU9 and applied our proposed techniques. We verified that operations were stopped at a rate of 49.1%, recognition accuracy was degraded by 0.29%, power consumption was reduced from 9.2 to 4.4 W (52.3%), and circuit overhead was reduced from 5.1 to 2.7% (45.9%). The proposed techniques were determined to be effective for lowering the power consumption of CNNbased edge devices such as FPGA.


