Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems

Yuan HE  Yasutaka WADA  Wenchao LUO  Ryuichi SAKAMOTO  Guanqin PAN  Thang CAO  Masaaki KONDO  

IEICE TRANSACTIONS on Electronics   Vol.E104-C   No.6   pp.237-246
Publication Date: 2021/06/01
Publicized: 2020/12/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2020LHP0005
Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
HPC,  performance,  power,  profiling,  modeling,  capping,  

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Due to the slowdown of Moore's Law, power limitation has been one of the most critical issues for current and future HPC systems. To more efficiently utilize HPC systems when power budgets or deadlines are given, it is very desirable to accurately estimate the performance or power consumption of applications before conducting their tuned production runs on any specific systems. In order to ease such estimations, we showcase a straight-forward and yet effective method, based on the enhanced power management framework and DSL we developed, to help HPC users to clarify the performance and power relationships of their applications. This method demonstrates an easy process of profiling, modeling and management on both performance and power of HPC systems and applications. In our evaluations, only a few (up to 3) profiled runs are necessary before very precise models of HPC applications can be obtained through this method (and algorithm), which has dramatically improved the efficiency of and lowered the difficulty in utilizing HPC systems under limited power budgets.