A Noise-Canceling Charge Pump for Area Efficient PLL Design

Go URAKAWA  Hiroyuki KOBAYASHI  Jun DEGUCHI  Ryuichi FUJIMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E104-C    No.10    pp.625-634
Publication Date: 2021/10/01
Publicized: 2021/04/20
Online ISSN: 1745-1353
DOI: 10.1587/transele.2020CTP0004
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
PLL,  frequency synthesizer,  phase-locked loop,  charge pump,  noise-cancel,  phase noise,  jitter,  in-band noise,  occupied area,  

Full Text: FreePDF

Summary: 
In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.