IEICE Trans - Gate Array Using Low-Temperature Poly-Si Thin-Film Transistors

Gate Array Using Low-Temperature Poly-Si Thin-Film Transistors

Mutsumi KIMURA  Masashi INOUE  Tokiyoshi MATSUDA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E103-C   No.7   pp.341-344
Publication Date: 2020/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2018ECP5067
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword:
gate array,  low-temperature poly-Si (LTPS),  thin-film transistor (TFT),

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Summary:
We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.