Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture

Ken NAKAMURA  Daisuke KOBAYASHI  Yuya OMORI  Tatsuya OSAWA  Takayuki ONISHI  Koyo NITTA  Hiroe IWASAKI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E103-C   No.3   pp.77-84
Publication Date: 2020/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2019LHP0005
Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
HEVC,  decoder,  high frame rate,  temporal scalability,  

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Summary: 
In this paper, we describe a novel low-delay 4K 120-fps real-time HEVC decoder with a parallel processing architecture that conforms to the HEVC main 4:2:2 10 profile. It supports the hierarchical temporal scalable streams required for Ultra High Definition high-frame-rate broadcasting and also supports low-delay and high-bitrate decoding for video transmission uses. To achieve this support, the decoding processes are parallelized and pipelined at the frame level, slice level, and coding tree unit row level. The proposed decoder was implemented on three FPGAs operated at 133 and 150 MHz, and it achieved 300-Mbps stream decoding and 37-msec end-to-end delay with our concurrently developed 4K 120-fps encoder.