Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model

Kenshiro SATO  Dondee NAVARRO  Shinya SEKIZAKI  Yoshifumi ZOKA  Naoto YORINO  Hans Jürgen MATTAUSCH  Mitiko MIURA-MATTAUSCH  

IEICE TRANSACTIONS on Electronics   Vol.E103-C   No.3   pp.119-126
Publication Date: 2020/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2019ECP5010
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
compact model,  DC-AC converter,  device aging,  efficiency,  SiC-MOSFET,  

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The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.