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A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications
Zheng SUN Dingxin XU Hongye HUANG Zheng LI Hanli LIU Bangan LIU Jian PANG Teruki SOMEYA Atsushi SHIRANE Kenichi OKADA
IEICE TRANSACTIONS on Electronics
Publication Date: 2020/10/01
Online ISSN: 1745-1353
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: Electronic Circuits
on-chip, transformer, PGS, ultra-low-power, LC-VCO, supply pushing, KVDD, phase-noise, FoM, area, IoT,
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This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.