3D-HEVC Virtual View Synthesis Based on a Reconfigurable Architecture

Lin JIANG  Xin WU  Yun ZHU  Yu WANG  

Publication
IEICE TRANSACTIONS on Communications   Vol.E103-B   No.5   pp.618-626
Publication Date: 2020/05/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.2019EBP3105
Type of Manuscript: PAPER
Category: Multimedia Systems for Communications
Keyword: 
3D-High Efficiency Video Coding (3D-HEVC),  view synthesis reference software (VSRS),  hole filling,  reconfigurable,  

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Summary: 
For high definition (HD) videos, the 3D-High Efficiency Video Coding (3D-HEVC) reference algorithm incurs dramatically highly computation loads. Therefore, with the demands for the real-time processing of HD video, a hardware implementation is necessary. In this paper, a reconfigurable architecture is proposed that can support both median filtering preprocessing and mean filtering preprocessing to satisfy different scene depth maps. The architecture sends different instructions to the corresponding processing elements according to different scenarios. Mean filter is used to process near-range images, and median filter is used to process long-range images. The simulation results show that the designed architecture achieves an averaged PSNR of 34.55dB for the tested images. The hardware design for the proposed virtual view synthesis system operates at a maximum clock frequency of 160MHz on the BEE4 platform which is equipped with four Virtex-6 FF1759 LX550T Field-Programmable Gate Array (FPGA) for outputting 720p (1024×768) video at 124fps.