Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy

Jinghao YE  Masao YANAGISAWA  Youhua SHI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E103-A   No.9   pp.1063-1070
Publication Date: 2020/09/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.2019KEP0010
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
FIR filter,  area-power efficient,  faithfully truncated adder,  

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Summary: 
To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.