Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework

Foisal AHMED  Michihiro SHINTANI  Michiko INOUE  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E103-A   No.9   pp.1045-1053
Publication Date: 2020/09/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.2019KEP0014
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
field-programmable gate array (FPGA),  recycled FPGA detection,  compressed sensing,  FPGA fingerprinting,  

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Summary: 
Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.