Supporting Predictable Performance Guarantees for SMT Processors

Xin JIN  Ningmei YU  Yaoyang ZHOU  Bowen HUANG  Zihao YU  Xusheng ZHAN  Huizhe WANG  Sa WANG  Yungang BAO  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E103-A   No.6   pp.806-820
Publication Date: 2020/06/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.2019EAP1146
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SMT interference,  data center,  performance predictability,  quality of service (QoS),  

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Summary: 
Simultaneous multithreading (SMT) technology improves CPU throughput, but also causes unpredictable performance fluctuations for co-running workloads. Although recent major SMT processors have adopted some techniques to promote hardware support for quality-of-service (QoS), achieving both precise performance guarantees and high throughput on SMT architectures is still a challenging open problem. In this paper, we demonstrate through some comprehensive investigations on a cycle-accurate simulator that not only almost all in-core resources suffer from severe contention as workloads vary but also there is a non-linear relationship between performance and available quotas of resources. We consider these observations as the fundamental reason leading to the challenging problem above. Thus, we introduce QoSMT, a novel hardware scheme that leverages a closed-loop controlling mechanism consisting of detection, prediction and adjustment to enforce precise performance guarantees for specific targets, e.g. achieving 85%, 90% or 95% of the performance of a workload running alone respectively. We implement a prototype on GEM5 simulator. Experimental results show that the average control error is only 1.4%, 0.5% and 3.6%.