Sorting Matrix Architecture for Continuous Data Sequences

Meiting XUE  Huan ZHANG  Weijun LI  Feng YU  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E103-A   No.2   pp.542-546
Publication Date: 2020/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.2019EAL2133
Type of Manuscript: LETTER
Category: Algorithms and Data Structures
Keyword: 
data sorting,  variable-width,  variable-length,  hardware design,  pipeline and parallel,  

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Summary: 
Sorting is one of the most fundamental problems in mathematics and computer science. Because high-throughput and flexible sorting is a key requirement in modern databases, this paper presents efficient techniques for designing a high-throughput sorting matrix that supports continuous data sequences. There have been numerous studies on the optimization of sorting circuits on FPGA (field-programmable gate array) platforms. These studies focused on attaining high throughput for a single command with fixed data width. However, the architectures proposed do not meet the requirement of diversity for database data types. A sorting matrix architecture is thus proposed to overcome this problem. Our design consists of a matrix of identical basic sorting cells. The sorting cells work in a pipeline and in parallel, and the matrix can simultaneously process multiple data streams, which can be combined into a high-width single-channel data stream or low-width multiple-channel data streams. It can handle continuous sequences and allows for sorting variable-length data sequences. Its maximum throughput is approximately 1.4 GB/s for 32-bit sequences and approximately 2.5 GB/s for 64-bit sequences on our platform.