Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing

Nobutaka KITO  Ryota ODAKA  Kazuyoshi TAKAGI  

IEICE TRANSACTIONS on Electronics   Vol.E102-C   No.7   pp.607-611
Publication Date: 2019/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2018ECS6014
Type of Manuscript: BRIEF PAPER
Category: Superconducting Electronics
rapid single flux quantum circuit,  truncated multiplier,  pulse logic,  

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A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.