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Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity
Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA
IEICE TRANSACTIONS on Electronics
Publication Date: 2019/07/01
Online ISSN: 1745-1353
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
power integrity, signal integrity, multi-layered inductor,
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This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.