A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes

Takuji MIKI  Noriyuki MIURA  Makoto NAGATA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E102-C   No.7   pp.530-537
Publication Date: 2019/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2018CTP0012
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
hardware security,  physical random number,  random masking,  SAR ADC,  

Full Text: FreePDF(1.5MB)


Summary: 
This paper presents a low-power small-area-overhead physical random number generator utilizing SAR ADC embedded in sensor SoCs. An unpredictable random bit sequence is produced by an existing comparator in typical SAR ADCs, which results in little area overhead. Unlike the other comparator-based physical random number generator, this proposed technique does not require an offset calibration scheme since SAR binary search algorithm automatically converges the two input voltages of the comparator to balance the differential circuit pair. Although the randomness slightly depends on an quantization error due to sharing AD conversion scheme, the input signal distribution enhances the quality of random number bit sequence which can use for various security countermeasures such as masking techniques. Fabricated in 180nm CMOS, 1Mb/s random bit generator achieves high efficiency of 0.72pJ/bit with only 400μm2 area overhead, which occupies less than 0.5% of SAR ADC, while remaining 10-bit AD conversion function.