Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs

Arnab MUKHOPADHYAY  Tapas Kumar MAITI  Sandip BHATTACHARYA  Takahiro IIZUKA  Hideyuki KIKUCHIHARA  Mitiko MIURA-MATTAUSCH  Hafizur RAHAMAN  Sadayuki YOSHITOMI  Dondee NAVARRO  Hans Jürgen MATTAUSCH  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E102-C   No.6   pp.487-494
Publication Date: 2019/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2018ECP5046
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
MOSFET,  optimization,  power efficient circuit design,  CMOS,  short-channel effect,  transit delays,  

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Summary: 
This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.