For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs
Arnab MUKHOPADHYAY Tapas Kumar MAITI Sandip BHATTACHARYA Takahiro IIZUKA Hideyuki KIKUCHIHARA Mitiko MIURA-MATTAUSCH Hafizur RAHAMAN Sadayuki YOSHITOMI Dondee NAVARRO Hans Jürgen MATTAUSCH
IEICE TRANSACTIONS on Electronics
Publication Date: 2019/06/01
Online ISSN: 1745-1353
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
MOSFET, optimization, power efficient circuit design, CMOS, short-channel effect, transit delays,
Full Text: PDF(1.9MB)>>
This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.