A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock

Haosheng ZHANG  Aravind THARAYIL NARAYANAN  Hans HERDIAN  Bangan LIU  Rui WU  Atsushi SHIRANE  Kenichi OKADA  

IEICE TRANSACTIONS on Electronics   Vol.E102-C    No.4    pp.276-286
Publication Date: 2019/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2018CDP0010
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
VCO,  chip-scale atomic clock (CSAC),  power efficiency,  phase noise,  tank loading,  tail filter,  

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This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.