Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers

Yongwoon SONG  Dongkeon CHOI  Hyukjun LEE  

IEICE TRANSACTIONS on Electronics   Vol.E102-C   No.12   pp.849-852
Publication Date: 2019/12/01
Publicized: 2019/06/25
Online ISSN: 1745-1353
DOI: 10.1587/transele.2019ECS6003
Type of Manuscript: BRIEF PAPER
Category: Integrated Electronics
packet buffer,  hybrid memory,  memory controller,  

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The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.