Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design

Po-Yu KUO  Chia-Hsin HSIEH  Jin-Fa LIN  Ming-Hwa SHEU  Yi-Ting HUNG  

IEICE TRANSACTIONS on Electronics   Vol.E102-C   No.11   pp.833-838
Publication Date: 2019/11/01
Publicized: 2019/08/05
Online ISSN: 1745-1353
DOI: 10.1587/transele.2018ECP5059
Type of Manuscript: PAPER
Category: Electronic Circuits
low power,  sense-amplifier,  flip-flop,  pass transistor logic,  

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A novel low power sense-amplifier based flip-flop (FF) is presented. By using a simplified SRAM based latch design and pass transistor logic (PTL) circuit scheme, the transistor-count of the FF design is greatly reduced as well as leakage power performance. The performance claims are verified through extensive post-layout simulations. Compared to the conventional sense-amplifier FF design, the proposed circuit achieves 19.6% leakage reduction. Moreover, the delay, and area are reduced by 21.8% and 31%, respectively. The performance edge becomes even better when the flip-flop is integrated in N-bit register file.