A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation

Leilei HUANG  Yibo FAN  Chenhao GU  Xiaoyang ZENG  

IEICE TRANSACTIONS on Electronics   Vol.E102-C   No.10   pp.756-765
Publication Date: 2019/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2018ECP5077
Type of Manuscript: PAPER
Category: Integrated Electronics
high efficiency video coding (HEVC),  integer motion estimation (IME),  hardware implementation,  very large scale integration (VLSI),  

Full Text: PDF(2MB)>>
Buy this Article

High Efficiency Video Coding (HEVC) standard is now becoming one of the most widespread video coding standards in the world. As a successor of H.264 standard, it aims to provide a much superior encoding performance. To fulfill this goal, several new notations along with the corresponding computation processes are introduced by this standard. Among those computation processes, the integer motion estimation (IME) is one of bottlenecks due to the complex partitions of the inter prediction units (PU) and the large search window commonly adopted. Many algorithms have been proposed to address this issue and usually put emphasis on a large search window and great computation amount. However, the coding efforts should be related to the scenes. To be more specific, for relatively static videos, a small search window along with a simple search scheme should be adopted to reduce the time cost and power consumption. In view of this, a micro-code-based IME engine is proposed in this paper, which could be applied with search schemes of different complexity. To test the performance, three different search schemes based on this engine are designed and evaluated under HEVC test model (HM) 16.9, achieving a B-D rate increase of 0.55/-0.07/-0.14%. Compared with our previous work, the hardware implementation is optimized to reduce 64.2% of the SRAMs bits and 32.8% of the logic gate count. The final design could support 4K×2K @139/85/37fps videos @500MHz.