Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches

Junnan LI  Biao HAN  Zhigang SUN  Tao LI  Xiaoyan WANG  

IEICE TRANSACTIONS on Communications   Vol.E102-B   No.9   pp.1862-1874
Publication Date: 2019/09/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.2018EBP3333
Type of Manuscript: PAPER
Category: Transmission Systems and Transmission Equipment for Communications
FPGA,  packet parsing,  packet-level parallelism,  programable parser,  

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FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.