Performance of Iterative Digital Self-Interference Canceler with Alternating Estimate Subtraction for OFDM Using Full Duplex

Takahiro OHTOMO
Keisuke SAITO

IEICE TRANSACTIONS on Communications   Vol.E102-B    No.8    pp.1490-1502
Publication Date: 2019/08/01
Publicized: 2019/02/20
Online ISSN: 1745-1345
DOI: 10.1587/transcom.2018TTP0018
Type of Manuscript: Special Section PAPER (Special Section on Technology Trials and Proof-of-Concept Activities for 5G and Beyond)
full duplex,  self-interference,  RF circuit response,  digital self-interference canceler,  

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In full duplex (FD), which improves the system capacity (or cell throughput) and reduces the transmission delay (or latency) through simultaneous transmission and reception in the same frequency band, self-interference (SI) from the transmitter should be suppressed using antenna isolation, an analog SI canceler, and digital SI canceler (DSIC) to a level such that the data or control channel satisfies the required block error rate (BLER). This paper proposes a structure of iterative DSIC with alternating estimate subtraction (AES-IDSIC) for orthogonal frequency division multiplexing (OFDM) using FD. We first present the required SI suppression level considering SI, quantization noise of an analog-to-digital converter, and nonlinear distortion of a power amplifier and RF receiver circuit for a direct conversion transceiver using FD. Then, we propose an AES-IDSIC structure that iterates the generation of the SI estimate, the downlink symbol estimate, and then alternately removes one of the estimates from the received signal in the downlink including SI. We investigate the average BLER performance of the AES-IDSIC for OFDM using FD in a multipath fading channel based on link-level simulations under the constraint that the derived required signal-to-SI ratio must be satisfied.