Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation

Renyuan ZHANG  Takashi NAKADA  Yasuhiko NAKASHIMA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E102-A   No.7   pp.878-885
Publication Date: 2019/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E102.A.878
Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
approximate computing,  analog calculation unit,  support vector regression,  vector-computation,  

Full Text: FreePDF(1.9MB)


Summary: 
A programmable analog calculation unit (ACU) is designed for vector computations in continuous-time with compact circuit scale. From our early study, it is feasible to retrieve arbitrary two-variable functions through support vector regression (SVR) in silicon. In this work, the dimensions of regression are expanded for vector computations. However, the hardware cost and computing error greatly increase along with the expansion of dimensions. A two-stage architecture is proposed to organize multiple ACUs for high dimensional regression. The computation of high dimensional vectors is separated into several computations of lower dimensional vectors, which are implemented by the free combination of several ACUs with lower cost. In this manner, the circuit scale and regression error are reduced. The proof-of-concept ACU is designed and simulated in a 0.18μm technology. From the circuit simulation results, all the demonstrated calculations with nine operands are executed without iterative clock cycles by 4960 transistors. The calculation error of example functions is below 8.7%.