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Hardware-Aware Sum-Product Decoding in the Decision Domain
Mizuki YAMADA Keigo TAKEUCHI Kiyoyuki KOIKE
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/12/01
Online ISSN: 1745-1337
Type of Manuscript: PAPER
Category: Coding Theory
low-density parity-check (LDPC) codes, sum-product (SP) decoding, hardware implementation, decision domain, polynomial approximation,
Full Text: FreePDF(1.3MB)
We propose hardware-aware sum-product (SP) decoding for low-density parity-check codes. To simplify an implementation using a fixed-point number representation, we transform SP decoding in the logarithm domain to that in the decision domain. A polynomial approximation is proposed to implement an update rule of the proposed SP decoding efficiently. Numerical simulations show that the approximate SP decoding achieves almost the same performance as the exact SP decoding when an appropriate degree in the polynomial approximation is used, that it improves the convergence properties of SP and normalized min-sum decoding in the high signal-to-noise ratio regime, and that it is robust against quantization errors.