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Design of LowCost Approximate Multipliers Based on ProbabilityDriven Inexact Compressors
Yi GUO Heming SUN Ping LEI Shinji KIMURA
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E102A
No.12
pp.17811791 Publication Date: 2019/12/01 Online ISSN: 17451337
DOI: 10.1587/transfun.E102.A.1781 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: approximate computing, inexact compressor, multiplier, error recovery,
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Summary:
Approximate computing has emerged as a promising approach for errortolerant applications to improve hardware performance at the cost of some loss of accuracy. Multiplication is a key arithmetic operation in these applications. In this paper, we propose a lowcost approximate multiplier design by employing new probabilitydriven inexact compressors. This compressor design is introduced to reduce the height of partial product matrix into two rows, based on the probability distribution of the sum result of partial products. To compensate the accuracy loss of the multiplier, a grouped error recovery scheme is proposed and achieves different levels of accuracy. In terms of mean relative error distance (MRED), the accuracy losses of the proposed multipliers are from 1.07% to 7.86%. Compared with the Wallace multiplier using 40nm process, the most accurate variant of the proposed multipliers can reduce power by 59.75% and area by 42.47%. The critical path delay reduction is larger than 12.78%. The proposed multiplier design has a better accuracyperformance tradeoff than other designs with comparable accuracy. In addition, the efficiency of the proposed multiplier design is assessed in an image processing application.

