Weighted Bit-Flipping Decoding of LDPC Codes with LLR Adjustment for MLC Flash Memories

Xuan ZHANG  Xiaopeng JIAO  Yu-Cheng HE  Jianjun MU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E102-A   No.11   pp.1571-1574
Publication Date: 2019/11/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E102.A.1571
Type of Manuscript: LETTER
Category: Digital Signal Processing
multi-level cell (MLC),  cell-to-cell interference,  LDPC codes,  weighted bit-flipping decoding,  

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Low-density parity-check (LDPC) codes can be used to improve the storage reliability of multi-level cell (MLC) flash memories because of their strong error-correcting capability. In order to improve the weighted bit-flipping (WBF) decoding of LDPC codes in MLC flash memories with cell-to-cell interference (CCI), we propose two strategies of normalizing weights and adjusting log-likelihood ratio (LLR) values. Simulation results show that the WBF decoding under the proposed strategies is much advantageous in both error and convergence performances over existing WBF decoding algorithms. Based on complexity analysis, the strategies provide the WBF decoding with a good tradeoff between performance and complexity.