Evaluation of Register Number Abstraction for Enhanced Instruction Register Files

Naoki FUJIEDA  Kiyohiro SATO  Ryodai IWAMOTO  Shuichi ICHIKAWA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E101-D   No.6   pp.1521-1531
Publication Date: 2018/06/01
Publicized: 2018/03/14
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2017EDP7221
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
computer architecture,  embedded systems,  instruction register files,  secure processors,  

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Summary: 
Instruction set randomization (ISR) is a cost-effective obfuscation technique that modifies or enhances the relationship between instructions and machine languages. An Instruction Register File (IRF), a list of frequently used instructions, can be used for ISR by providing the way of indirect access to them. This study examines the IRF that integrates a positional register, which was proposed as a supplementary unit of the IRF, for the sake of tamper resistance. According to our evaluation, with a new design for the contents of the positional register, the measure of tamper resistance was increased by 8.2% at a maximum, which corresponds to a 32.2% increase in the size of the IRF. The number of logic elements increased by the addition of the positional register was 3.5% of its baseline processor.