Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device

Toshihiro KATASHITA  Masakazu HIOKI  Yohei HORI  Hanpei KOIKE  

IEICE TRANSACTIONS on Information and Systems   Vol.E101-D   No.2   pp.303-313
Publication Date: 2018/02/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2017RCP0003
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Device and Architecture
FPGA,  programmable body biasing,  evaluation platform,  static power consumption,  

Full Text: PDF(4MB)>>
Buy this Article

Field-programmable gate array (FPGA) devices are applied for accelerating specific calculations and reducing power consumption in a wide range of areas. One of the challenges associated with FPGAs is reducing static power for enforcing their power effectiveness. We propose a method involving fine-grained reconfiguration of body biases of logic and net resources to reduce the static power of FPGA devices. In addition, we develop an FPGA device called Flex Power FPGA with SOTB technology and demonstrate its power reduction function with a 32-bit counter circuit. In this paper, we describe the construction of an experimental platform to precisely evaluate power consumption and the maximum operating frequency of the device under various operating voltages and body biases with various practical circuits. Using the abovementioned platform, we evaluate the Flex Power FPGA chip at operating voltages of 0.5-1.0 V and at body biases of 0.0-0.5 V. In the evaluation, we use a 32-bit adder, 16-bit multiplier, and an SBOX circuit for AES cryptography. We operate the chip virtually with uniformed body bias voltage to drive all of the logic resources with the same threshold voltage. We demonstrate the advantage of the Flex Power FPGA by comparing its performance with non-reconfigurable biasing.