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Lightweight Security Hardware Architecture Using DWT and AES Algorithms
Ignacio ALGREDO-BADILLO Francisco R. CASTILLO-SORIA Kelsey A. RAMÍREZ-GUTIÉRREZ Luis MORALES-ROSALES Alejandro MEDINA-SANTIAGO Claudia FEREGRINO-URIBE
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2018/11/01
Online ISSN: 1745-1361
Type of Manuscript: PAPER
Category: Information Network
hardware, steganography, cryptography, DWT, FPGA,
Full Text: PDF(1.4MB)>>
The great increase of the digital communications, where the technological society depends on applications, devices and networks, the security problems motivate different researches for providing algorithms and systems resistant to attacks, and these lasts need of services of confidentiality, authentication, integrity, etc. This paper proposes the hardware implementation of an steganographic/cryptographic algorithm, which is based on the DWT (Discrete Wavelet Transform) and the AES (Advanced Encryption Standard) cipher algorithm in CBC mode. The proposed scheme takes advantage of a double-security ciphertext, which makes difficult to identify and decipher it. The hardware architecture reports a high efficiency (182.2 bps/slice and 85.2 bps/LUT) and low hardware resources consumption (867 slices and 1853 LUTs), where several parallel implementations can improve the throughout (0.162 Mbps) for processing large amounts of data.