A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique

Takayuki OKAZAWA  Ippei AKITA  

IEICE TRANSACTIONS on Electronics   Vol.E101-C   No.5   pp.396-403
Publication Date: 2018/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.396
Type of Manuscript: PAPER
Category: Integrated Electronics
dynamic latched comparator,  self-calibrating,  stochastic offset voltage detection,  

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This paper presents a self-calibrating dynamic latched comparator with a stochastic offset voltage detector that can be realized by using simple digital circuitry. An offset voltage of the comparator is compensated by using a statistical calibration scheme, and the offset voltage detector uses the uncertainty in the comparator output. Thanks to the simple offset detection technique, all the calibration circuitry can be synthesized using only standard logic cells. This paper also gives a design methodology that can provide the optimal design parameters for the detector on the basis of fundamental statistics, and the correctness of the design methodology was statistically validated through measurement. The proposed self-calibrating comparator system was fabricated in a 180 nm 1P6M CMOS process. The prototype achieved a 38 times improvement in the three-sigma of the offset voltage from 6.01 mV to 158 µV.