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Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing
Koki ISHIDA Masamitsu TANAKA Takatsugu ONO Koji INOUE
IEICE TRANSACTIONS on Electronics
Publication Date: 2018/05/01
Online ISSN: 1745-1353
Type of Manuscript: INVITED PAPER (Special Section on Innovative Superconducting Devices Based on New Physical Phenomena)
single flux quantum (SFQ), cryogenic computing, microprocessor, cache memory, Josephson junction, low-power, high-performance, energy-efficient,
Full Text: FreePDF(1.3MB)
CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.