IEICE Trans - Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB

Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB

Miseon HAN
Yeoul NA
Dongha JUNG
Hokyoon LEE
Seon WOOK KIM
Youngsun HAN

Publication
IEICE TRANSACTIONS on Electronics Vol.E101-C No.3 pp.170-182
Publication Date: 2018/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.170
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword:
DRAM, selective refresh, power reduction, EDP,

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Summary:
A memory controller refreshes DRAM rows periodically in order to prevent DRAM cells from losing data over time. Refreshes consume a large amount of energy, and the problem becomes worse with the future larger DRAM capacity. Previously proposed selective refreshing techniques are either conservative in exploiting the opportunity or expensive in terms of required implementation overhead. In this paper, we propose a novel DRAM selective refresh technique by using page residence in a memory hierarchy of hardware-managed TLB. Our technique maximizes the opportunity to optimize refreshing by activating/deactivating refreshes for DRAM pages when their PTEs are inserted to/evicted from TLB or data caches, while the implementation cost is minimized by slightly extending the existing infrastructure. Our experiment shows that the proposed technique can reduce DRAM refresh power 43.6% on average and EDP 3.5% with small amount of hardware overhead.