Modeling and Layout Optimization of MOM Capacitor for High-Frequency Applications

Yuka ITANO  Taishi KITANO  Yuta SAKAMOTO  Kiyotaka KOMOKU  Takayuki MORISHITA  Nobuyuki ITOH  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E101-A   No.2   pp.441-446
Publication Date: 2018/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E101.A.441
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
MOM capacitor,  parasitic resistance,  parasitic inductance,  layout optimization,  

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In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.