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Two-Step Column-Parallel SAR/Single-Slope ADC for CMOS Image Sensors
Hejiu ZHANG Ningmei YU Nan LYU Keren LI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2018/02/01
Online ISSN: 1745-1337
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
A/D conversion, column-parallel ADC, SAR/single-slope ADC, CMOS image sensor,
Full Text: PDF(838.4KB)>>
This letter presents a 12-bit column-parallel hybrid two-step successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). For achieving a high conversion speed, a simple SAR ADC is used in upper 6-bit conversion and a conventional SS ADC is used in lower 6-bit conversion. To reduce the power consumption, a comparator is shared in each column, and a 6-bit ramp generator is shared by all columns. This ADC is designed in SMIC 0.18µm CMOS process. At a clock frequency of 22.7MHz, the conversion time is 3.2µs. The ADC has a DNL of -0.31/+0.38LSB and an INL of -0.86/+0.8LSB. The power consumption of each column ADC is 89µW and the ramp generator is 763µW.