A 2nd-Order ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase

Chunhui PAN  Hao SAN  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E101-A    No.2    pp.425-433
Publication Date: 2018/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E101.A.425
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
ΔΣ modulator,  ring amplifier,  switched-capacitor circuit,  successive-approximation-register ADC (SAR ADC),  

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A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation phase using ring amplifier and SAR quantizer. The proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order ΔΣAD modulator in 90nm CMOS technology. Simulated SNDR of 95.70dB is achieved while a sinusoid -1dBFS input is sampled at 60MS/s for the bandwidth is BW=470kHz. The power consumption of the analog part in the modulator is 1.67mW while the supply voltage is 1.2V.