IEICE Trans - Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis

Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis

Shinichi NISHIZAWA  Hidetoshi ONODERA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E101-A    No.12    pp.2222-2230
Publication Date: 2018/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E101.A.2222
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
D-Flip-Flop,  variation aware design,  regression analysis,

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Summary:
This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.