A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line

Yoshinobu HIGAMI  Senling WANG  Hiroshi TAKAHASHI  Shin-ya KOBAYASHI  Kewal K. SALUJA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E100-D   No.9   pp.2224-2227
Publication Date: 2017/09/01
Publicized: 2017/06/12
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2016EDL8210
Type of Manuscript: LETTER
Category: Dependable Computing
Keyword: 
fault diagnosis,  bridging faults,  clock lines,  

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Summary: 
In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.