Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Motoki AMAGASAKI  Yuki NISHITANI  Kazuki INOUE  Masahiro IIDA  Morihiro KUGA  Toshinori SUEYOSHI  

IEICE TRANSACTIONS on Information and Systems   Vol.E100-D   No.4   pp.633-644
Publication Date: 2017/04/01
Publicized: 2017/01/13
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2016AWI0005
Type of Manuscript: INVITED PAPER (Special Section on Award-winning Papers)
fault tolerant,  fault recovery,  FPGA-IP,  

Full Text: FreePDF(2.6MB)

Fault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area.