IEICE Trans - LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

Yu HU  Jing YE  Zhiping SHI  Xiaowei LI

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E100-D   No.2   pp.323-331
Publication Date: 2017/02/01
Publicized: 2016/10/25
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2016EDP7184
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword:
process variation,  timing variation,  sample,  path selection,  least square,

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Summary:
Process variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.