IEICE Trans - A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS

Takuji MIKI
Noriyuki MIURA
Kento MIZUTA
Shiro DOSHO
Makoto NAGATA

Publication
IEICE TRANSACTIONS on Electronics Vol.E100-C No.6 pp.560-567
Publication Date: 2017/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E100.C.560
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category:
Keyword:
Voltage-to-Time converter (VTC), time domain processing, CMOS, two-step transition, trip voltage,

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Summary:
In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um² silicon area and consumes 0.18 mW at 1 GS/s.