Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs

Soyeon JOO  Jintae KIM  SoYoung KIM  

IEICE TRANSACTIONS on Electronics   Vol.E100-C   No.5   pp.504-512
Publication Date: 2017/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E100.C.504
Type of Manuscript: PAPER
Category: Electronic Circuits
power-supply rejection (PSR),  low drop-out (LDO) regulator,  pass transistor,  two-stage op-amp,  

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This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.