For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs
Soyeon JOO Jintae KIM SoYoung KIM
IEICE TRANSACTIONS on Electronics
Publication Date: 2017/05/01
Online ISSN: 1745-1353
Type of Manuscript: PAPER
Category: Electronic Circuits
power-supply rejection (PSR), low drop-out (LDO) regulator, pass transistor, two-stage op-amp,
Full Text: PDF(2.1MB)>>
This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.