A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display

Ho-Seong KIM  Pil-Ho LEE  Jin-Wook HAN  Seung-Hun SHIN  Seung-Wuk BAEK  Doo-Ill PARK  Yongkyu SEO  Young-Chan JANG  

IEICE TRANSACTIONS on Electronics   Vol.E100-C   No.11   pp.1035-1038
Publication Date: 2017/11/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E100.C.1035
Type of Manuscript: BRIEF PAPER
transmitter bridge chip,  MIPI D-PHY,  DSI,  FPGA-based frame generator,  phase-locked loop,  

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A 10 Gbps transmitter bridge chip including four data lanes, which increases the bandwidth using an 8-to-1 serialization, is proposed for a field-programmable gate array (FPGA)-based frame generator to support the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) display serial interface (DSI).