IEICE Trans - AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures

AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures

Xuan-Tu TRAN  Tung NGUYEN  Hai-Phong PHAN  Duy-Hieu BUI

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E100-A   No.8   pp.1650-1660
Publication Date: 2017/08/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E100.A.1650
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword:
network-on-chip,  network interface,  AMBA eXtensible interface (AXI),

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Summary:
The increasing demand on scalability and reusability of system-on-chip design as well as the decoupling between computation and communication has motivated the growth of the Network-on-Chip (NoC) paradigm in the last decade. In NoC-based systems, the computational resources (i.e. IPs) communicate with each other using a network infrastructure. Many works have focused on the development of NoC architectures and routing mechanisms, while the interfacing between network and associated IPs also needs to be considered. In this paper, we present a novel efficient AXI (AMBA eXtensible Interface) compliant network adapter for NoC architectures, which is named an AXI-NoC adapter. The proposed network adapter achieves high communication throughput of 20.8Gbits/s and consumes 4.14mW at the operating frequency of 650MHz. It has a low area footprint (952 gates, approximate to 2,793µm² with CMOS 45nm technology) thanks to its effective hybrid micro-architectures and with zero latency thanks to the proposed mux-selection method.