Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor

Yu SUZUKI  Masato ITO  Satoshi KANDA  Kousuke IMAMURA  Yoshio MATSUDA  Tetsuya MATSUMURA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E100-A   No.12   pp.2888-2900
Publication Date: 2017/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E100.A.2888
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
optical flow,  HOE algorithm,  SOR,  FPGA,  processor,  

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This paper describes the design and implementation of a real-time optical flow processor using a single field-programmable gate array (FPGA) chip. By introducing the modified initial flow generation method, the successive over-relaxation (SOR) method for both layers, the optimization of the reciprocal operation method, and the image division method, it is now possible to both reduce hardware requirements and improve flow accuracy. Additionally, by introducing a pipeline structure to this processor, high-throughput hardware implementation could be achieved. Total logic cell (LC) amounts and processer memory capacity are reduced by about 8% and 16%, respectively, compared to our previous hierarchical optical flow estimation (HOE) processor. The results of our evaluation confirm that this processor can perform 30 fps wide extended graphics array (WXGA) 175.7MHz real-time optical flow processing with a single FPGA.