A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems

Seiji MOCHIZUKI  Katsushige MATSUBARA  Keisuke MATSUMOTO  Chi Lan Phuong NGUYEN  Tetsuya SHIBAYAMA  Kenichi IWATA  Katsuya MIZUMOTO  Takahiro IRITA  Hirotaka HARA  Toshihiro HATTORI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E100-A   No.12   pp.2878-2887
Publication Date: 2017/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E100.A.2878
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
video processing,  automotive,  low latency,  memory-access-data compression,  

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Summary: 
A 197mW 70ms-latency Full-HD 12-channel video-processing SoC for in-vehicle information systems has been implemented in 16nm CMOS. The SoC integrates 17 video processors of 6 types to operate video processing independently of other processing in CPU/GPU. The synchronous scheme between the video processors achieves 70ms low-latency for driver assistance. The optimized implementation of lossy and lossless video-data compression reduces memory access data by half and power consumption by 20%.