Worst-Case Performance of ILIFC with Inversion Cells

Akira YAMAWAKI  Hiroshi KAMABE  Shan LU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E100-A   No.12   pp.2662-2670
Publication Date: 2017/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E100.A.2662
Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory for Strage
flash memory,  block erasure,  index-less indexed flash code,  

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Index-less Indexed Flash Code (ILIFC) is a coding scheme for flash memories in which one bit of a data sequence is stored in a slice consisting of several cells but the index of the bit is stored implicitly. Although several modified ILIFC schemes have been proposed, in this research we consider an ILIFC with inversion cells (I-ILIFC). The I-ILIFC reduces the total number of cell level changes at each write request. Computer simulation is used to show that the I-ILIFC improves the average performance of the ILIFC in many cases. This paper presents our derivation of the lower bound on the number of write operations by I-ILIFC and shows that the worst-case performance of the I-ILIFC is better than that of the ILIFC if the code length is sufficiently large. Additionally, we consider another lower bound thereon. The results show that the threshold of the code length that determines whether the I-ILIFC improves the worst-case performance of the ILIFC is lower than that in the first lower bound.