An Incremental Simulation Technique Based on Delta Model for Lifetime Yield Analysis

Nguyen Cao QUI
Si-Rong HE
Chien-Nan Jimmy LIU

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E100-A    No.11    pp.2370-2378
Publication Date: 2017/11/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E100.A.2370
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
delta circuit model,  incremental simulation,  lifetime yield reliability analysis,  

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As devices continue to shrink, the parameter shift due to process variation and aging effects has an increasing impact on the circuit yield and reliability. However, predicting how long a circuit can maintain its design yield above the design specification is difficult because the design yield changes during the aging process. Moreover, performing Monte Carlo (MC) simulation iteratively during aging analysis is infeasible. Therefore, most existing approaches ignore the continuity during simulations to obtain high speed, which may result in accumulation of extrapolation errors with time. In this paper, an incremental simulation technique is proposed for lifetime yield analysis to improve the simulation speed while maintaining the analysis accuracy. Because aging is often a gradual process, the proposed incremental technique is effective for reducing the simulation time. For yield analysis with degraded performance, this incremental technique also reduces the simulation time because each sample is the same circuit with small parameter changes in the MC analysis. When the proposed dynamic aging sampling technique is employed, 50× speedup can be obtained with almost no decline accuracy, which considerably improves the efficiency of lifetime yield analysis.

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