IEICE Trans

Keyword : yield

AuGe-Alloy Source and Drain Formation by the Lift-Off Process for the Scaling of Bottom-Contact Type Pentacene-Based OFETs Shun-ichiro OHMI Mizuha HIROKI Yasutaka MAEDA
Publication: Publication Date: 2019/02/01 Vol. E102-C No. 2 ; pp. 138-142 Type of Manuscript: Special Section PAPER (Special Section on Recent Progress in Organic Molecular Electronics and Biotechnology) Category: Keyword: AuGe, bottom-contact, pentacene, OFET, lift-off, yield, SPM cleaning, PMA process,
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Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator Md. Maruf HOSSAIN Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA
Publication: Publication Date: 2018/02/01 Vol. E101-A No. 2 ; pp. 410-424 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: sub-ranging ADC, stochastic comparator, yield, probability density function, optimization, calibration,
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A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement Hayato MASHIKO Yukihide KOHIRA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 ; pp. 2443-2450 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: delay variation, timing violation, yield, programmable delay element,
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Introduction of Yield Quadrant and Yield Capability Index for VLSI Manufacturing Junichi HIRASE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/06/01 Vol. E97-C No. 6 ; pp. 609-618 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: yield, cluster parameter, systematic yield, yield quadrant, yield capability index,
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Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis Shiho HAGIWARA Takanori DATE Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 ; pp. 280-288 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: design for manufacturing, Monte Carlo method, importance sampling, SRAM, process variation, yield, norm minimization, Gaussian mixture models, clustering, hypersphere sampling,
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An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs Tsu-Lin LI Masaki HASHIZUME Shyue-Kung LU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 ; pp. 2026-2030 Type of Manuscript: Special Section LETTER (Special Section on Dependable Computing) Category: Keyword: NROM, data inversion, fault masking, yield,
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A High Performance Current Latch Sense Amplifier with Vertical MOSFET Hyoungjun NA Tetsuo ENDOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/05/01 Vol. E96-C No. 5 ; pp. 655-662 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: current latch sense amplifier, vertical MOSFET, SRAM, sensing time, speed, current, voltage gain, stability, yield, circuit area,
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Yield-Ensuring DAC-Embedded Opamp Design Based on Accurate Behavioral Model Development Yeong-Shin JANG Hoai-Nam NGUYEN Seung-Tak RYU Sang-Gug LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 ; pp. 935-937 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: DAC, DAC-embedded, behavioral model, yield,
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A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations Kazutoshi KOBAYASHI Kazuya KATSUKI Manabu KOTANI Yuuri SUGIHARA Yohei KUME Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 ; pp. 1919-1926 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Low-Power and High-Performance VLSI Circuit Technology Keyword: variation-aware, reconfigurable device, FPGA, yield, DFM,
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A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 ; pp. 699-707 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: within-die variation, reconfigurable device, FPGA, LUT (look-up table), yield,
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Redundant Design for Wallace Multiplier Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/09/01 Vol. E89-D No. 9 ; pp. 2512-2524 Type of Manuscript: PAPER Category: Dependable Computing Keyword: Wallace multiplier, bit-slice reconfiguration redundant design, defect-tolerance, yield,
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Defect Level Prediction Using Multi-Model Fault Coverage Shyue-Kung LU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/06/01 Vol. E87-D No. 6 ; pp. 1488-1495 Type of Manuscript: PAPER Category: Dependable Computing Keyword: defect level, fault coverage, multi-model fault coverage, yield,
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Module Selection Using Manufacturing Information Hiroyuki TOMIYAMA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 ; pp. 2576-2584 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-level Synthesis Keyword: high-level synthesis, module selection, manufacturability, yield,
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Analyzing and Reducing the Impact of Shorter Data Retention Time on the Performance of Merged DRAM/Logic LSIs Koji KAI Akihiko INOUE Taku OHSAWA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 ; pp. 1448-1454 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: merged DRAM/logic LSIs, data retention time, refresh, yield,
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Highly Sensitive OBIRCH System for Fault Localization and Defect Detection Kiyoshi NIKAWA Shoji INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 ; pp. 743-748 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Beam Testing/Diagnosis Keyword: VLSI chip, fault localization, metal line defect detection, high resistivity, TiSi, Al, reliability, yield, failure analysis,
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Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement Hideyuki FUKUHARA Takao KOMATSUZAKI Katsushi BOKU Yoichi MIYAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 ; pp. 852-857 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: yield, random logic circuitry, defect, Monte Calro simulation,
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Estimation of Yield Suppression for 1.5 V-1 Gbit DRAMs Caused by Threshold Voltage Variation of MOSFET due to Microscopic Fluctuation in Dopant Distributions Shigeyoshi WATANABE Takaaki MINAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/02/25 Vol. E77-C No. 2 ; pp. 273-279 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 1 Gbit DRAM, 1.5 V, yield, threshold voltage variation, redundancy,
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Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement Ken-ichi IMAMIYA Jun-ichi MIYAMOTO Nobuaki OHTSUKA Naoto TOMITA Yumiko IYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 ; pp. 1626-1631 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Non-volatile Memory Keyword: redundancy, memory, yield, EPROM,
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